MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 311

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MC68HC708AS48
MOTOROLA
—
Rev. 4.0
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SPWOM — SPI Wired-OR Mode Bit
This read/write bit determines the logic state of the SPSCK pin
between transmissions. (See
transmit data between SPI modules, the SPI modules must have
identical CPOL bits. Reset clears the CPOL bit.
This read/write bit controls the timing relationship between the serial
clock and SPI data. (See
data between SPI modules, the SPI modules must have identical
CPHA bits. When CPHA = 0, the SS pin of the slave SPI module must
be set to logic 1 between bytes. (See
CPHA bit.
When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle
state and begin driving the MISO pin with the MSB of its data. Once
the transmission begins, no new data is allowed into the shift register
from the data register. Therefore, the slave data register must be
loaded with the desired transmit data before the falling edge of SS.
Any data written after the falling edge is stored in the data register and
transferred to the shift register at the current transmission.
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the
beginning of the transmission. The same applies when SS is high for
a slave. The MISO pin is held in a high-impedance state, and the
incoming SPSCK is ignored. In certain cases, it may also cause the
MODF flag to be set. (See
SS pin does not in any way affect the state of the SPI state machine.
This read/write bit disables the pullup devices on pins SPSCK, MOSI,
and MISO so that those pins become open-drain outputs.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
Serial Peripheral Interface (SPI)
Figure 18-4
18.7.2 Mode Fault
Figure 18-4
Figure
and
Serial Peripheral Interface (SPI)
and
Figure
18-12.) Reset sets the
Error.) A logic 1 on the
Figure
18-6.) To transmit
Advance Information
18-6.) To
I/O Registers
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