MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 22

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MC68HC708AS48

Manufacturer Part Number
MC68HC708AS48
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
List of Figures
Figure
16-7
16-8
16-9
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
17-11
17-12
17-13
17-14
17-15
17-16
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
18-15
Advance Information
22
Title
TIM Channel Status
and Control Registers (TSC0–TSC5) . . . . . . . . . . . . . .233
CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
TIM Channel Registers (TCH0H/L–TCH3H/L) . . . . . . . . . .239
SCI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .246
SCI I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . .247
SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
Transmitter I/O Register Summary. . . . . . . . . . . . . . . . . . .251
SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . .255
SCI Receiver I/O Register Summary . . . . . . . . . . . . . . . . .256
Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . .258
SCI Control Register 1 (SCC1) . . . . . . . . . . . . . . . . . . . . .266
SCI Control Register 2 (SCC2) . . . . . . . . . . . . . . . . . . . . .269
SCI Control Register 3 (SCC3) . . . . . . . . . . . . . . . . . . . . .272
SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . .274
Flag Clearing Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . .277
SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . .278
SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . .279
SCI BAUD Rate Register 1 (SCBR) . . . . . . . . . . . . . . . . . .280
SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .286
SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .287
Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . .288
Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . .291
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292
Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . .293
Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . .295
Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . .297
Clearing SPRF When OVRF Interrupt Is Not Enabled . . . .298
SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . .301
SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . .302
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . .310
SPI Status and Control Register (SPSCR). . . . . . . . . . . . .313
SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . .316
List of Figures
Page
MC68HC708AS48
Rev. 4.0
MOTOROLA

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