MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 23

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MC68HC708AS48
MOTOROLA
—
Rev. 4.0
Figure
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ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319
ADC Status and Control Register (ADSCR). . . . . . . . . . . .324
ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . .327
ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . .327
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
BDLC Input/Output (I/O) Register Summary . . . . . . . . . . .333
BDLC Operating Modes State Diagram . . . . . . . . . . . . . . .334
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
BDLC Rx Digital Filter Block Diagram . . . . . . . . . . . . . . . .338
J1850 Bus Message Format (VPW). . . . . . . . . . . . . . . . . .340
J1850 VPW Symbols with Nominal Symbol Times . . . . . .344
J1850 VPW Received Passive Symbol Times . . . . . . . . . .347
J1850 VPW Received Passive
J1850 VPW Received Active Symbol Times . . . . . . . . . . .349
J1850 VPW Received BREAK Symbol Times . . . . . . . . . .350
J1850 VPW Bitwise Arbitrations. . . . . . . . . . . . . . . . . . . . .351
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
BDLC Protocol Handler Outline . . . . . . . . . . . . . . . . . . . . .353
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
BDLC Analog and Roundtrip Delay Register (BARD) . . . .358
BDLC Control Register 1 (BCR1) . . . . . . . . . . . . . . . . . . . .360
BDLC Control Register 2 (BCR2) . . . . . . . . . . . . . . . . . . . .363
Types of In-Frame Response (IFR) . . . . . . . . . . . . . . . . . .367
BDLC State Vector Register (BSVR) . . . . . . . . . . . . . . . . .371
BDLC Data Register (BDR) . . . . . . . . . . . . . . . . . . . . . . . .373
SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384
SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385
BDLC Variable Pulse Width Modulation (VPW)
EOF and IFS Symbol Times . . . . . . . . . . . . . . . . . . . . .348
Symbol Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389
List of Figures
Title
Advance Information
List of Figures
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