MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 110

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Clock Generator Module (CGM)
8.5.4 Analog Power Pin (V
8.5.5 Oscillator Enable Signal (SIMOSCEN)
8.5.6 Crystal Output Frequency Signal (CGMXCLK)
8.5.7 CGM Base Clock Output (CGMOUT)
8.5.8 CGM CPU Interrupt (CGMINT)
Advance Information
110
NOTE:
V
Connect the V
pin.
Route V
bypass capacitors as close as possible to the package.
The SIMOSCEN signal comes from the system integration module (SIM)
and enables the oscillator and PLL.
CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal, f
Figure 8-3
OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
CGMOUT is the clock output of the CGM. This signal goes to the SIM,
which generates the MCU clocks. CGMOUT is a 50% duty cycle clock
running at twice the bus frequency. CGMOUT is software programmable
to be either the oscillator output, CGMXCLK, divided by two or the VCO
clock, CGMVCLK, divided by two.
CGMINT is the interrupt signal generated by the PLL lock detector.
DDA
DDA
/V
DDAREF
DDA
/V
Clock Generator Module (CGM)
DDAREF
shows only the logical relation of CGMXCLK to OSC1 and
/V
DDA
DDAREF
XCLK
is a power pin used by the analog portions of the PLL.
/V
)
, and comes directly from the crystal oscillator circuit.
DDAREF
carefully for maximum noise immunity and place
pin to the same voltage potential as the V
MC68HC708AS48
MOTOROLA
—
Rev. 4.0
DD