MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 238

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Timer Interface (TIM)
16.9.5 TIM Channel Registers
Advance Information
238
CHxMAX — Channel x Maximum Duty Cycle Bit
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
PTEx/TCHx
CHxMAX
When the TOVx bit is at logic 0, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 16-8
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
OVERFLOW
Timer Interface (TIM)
COMPARE
shows, the CHxMAX bit takes effect in the cycle after it
PERIOD
OUTPUT
Figure 16-8. CHxMAX Latency
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
MC68HC708AS48
OVERFLOW
COMPARE
OUTPUT
MOTOROLA
OVERFLOW
—
Rev. 4.0