MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 151

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MC68HC708AS48

Manufacturer Part Number
MC68HC708AS48
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Addr.
Register Name
LVI Status Register
$FE0F
(LVISR)
10.4.1 Polled LVI Operation
In applications that can operate at V
software can monitor V
register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
10.4.2 Forced Reset Operation
In applications that require V
LVI resets allows the LVI module to reset the MCU when V
V
LVII
must be at logic 0 to enable the LVI module and to enable LVI resets.
MC68HC708AS48
Rev. 4.0
MOTOROLA
Bit 7
6
5
Read: LVIOUT
0
0
Write:
R
R
R
Reset:
0
0
0
R
= Reserved
Figure 10-2. LVI I/O Register Summary
by polling the LVIOUT bit. In the CONFIG
DD
DD
level. In the CONFIG register, the LVIPWRD and LVIRSTD bits
Low-Voltage Inhibit (LVI)
Low-Voltage Inhibit (LVI)
Functional Description
4
3
2
0
LVISTOP LVILCK
R
0
0
0
levels below the V
DD
LVII
to remain above the V
level, enabling
LVII
Advance Information
1
Bit 0
0
0
R
R
0
0
level,
falls to the
DD
151

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