MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 337

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

20.5 BDLC MUX Interface
MC68HC708AS48
MOTOROLA
—
Rev. 4.0
to the J1850 bus typically is high impedance. This allows the
communication path through the analog transceiver to be tested without
interfering with network activity. Using the BDLC analog loopback mode
in conjunction with the analog transceiver’s loopback mode ensures
that, once the off-chip analog transceiver has exited loopback mode, the
BCLD will not begin communicating before a known condition exists on
the J1850 bus.
The MUX interface is responsible for bit encoding/decoding and digital
noise filtering between the protocol handler and the physical interface.
Byte Data Link Controller–Digital (BDLC–D)
Figure 20-4. BDLC Block Diagram
PHYSICAL INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
CPU INTERFACE
TO J1850 BUS
TO CPU
Byte Data Link Controller–Digital (BDLC–D)
BDLC
BDLC MUX Interface
Advance Information
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