MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 344

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Byte Data Link Controller–Digital (BDLC–D)
Advance Information
344
ACTIVE
PASSIVE
ACTIVE
PASSIVE
Figure 20-7. J1850 VPW Symbols with Nominal Symbol Times
ACTIVE
PASSIVE
ACTIVE
PASSIVE
(F) END OF FRAME
(C) BREAK
240 s
280 s
Logic 0
A logic 0 is defined as either:
See
Byte Data Link Controller–Digital (BDLC–D)
– An active-to-passive transition followed by a passive period
– A passive-to-active transition followed by an active period
Figure
64 s in length, or
128 s in length
(G) INTER-FRAME
SEPARATION
20-7(a).
128 s
128 s
20 s
300 s
(A) LOGIC 0
(B) LOGIC 1
(D) START OF FRAME
200 s
OR
OR
IDLE > 300 s
(H) IDLE
MC68HC708AS48
64 s
64 s
(E) END OF DATA
200 s
MOTOROLA
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Rev. 4.0