MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 358

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Byte Data Link Controller–Digital (BDLC–D)
20.7 BDLC CPU Interface
20.7.1 BDLC Analog and Roundtrip Delay
Advance Information
358
Address:
Figure 20-16. BDLC Analog and Roundtrip Delay Register (BARD)
The CPU interface provides the interface between the CPU and the
BDLC and consists of five user registers.
This register programs the BDLC to compensate for various delays of
different external transceivers. The default delay value is 16 s. Timing
adjustments from 9 s to 24 s in steps of 1 s are available. The BARD
register can be written only once after each reset, after which they
become read-only bits. The register may be read at any time.
Reset:
Read:
Write:
Byte Data Link Controller–Digital (BDLC–D)
$003B
Bit 7
ATE
R
1
= Reserved
RXPOL
Figure 20-15. BDLC Block Diagram
6
1
R
5
0
0
PROTOCOL HANDLER
PHYSICAL INTERFACE
MUX INTERFACE
CPU INTERFACE
TO J1850 BUS
TO CPU
R
4
0
0
BO3
3
0
BDLC
MC68HC708AS48
BO2
2
1
BO1
1
1
MOTOROLA
—
Rev. 4.0
Bit 0
BO0
1