MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 258

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MC68HC708AS48

Manufacturer Part Number
MC68HC708AS48
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
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Serial Communications Interface (SCI)
17.4.12 Data Sampling
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258
PTE1/RxD
RT CLOCK
RT CLOCK
SAMPLES
CLOCK
RESET
STATE
RT
The receiver samples the PTE1/RxD pin at the RT clock rate. The RT
clock is an internal signal with a frequency 16 times the baud rate. To
adjust for baud rate mismatch, the RT clock is resynchronized at these
times (see
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
Figure 17-8. Receiver Data Sampling
QUALIFICATION
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
START BIT
Serial Communications Interface (SCI)
Figure
17-8):
VERIFICATION
START BIT
START BIT
SAMPLING
DATA
MC68HC708AS48
MOTOROLA
LSB
Rev. 4.0

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