MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 129

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

9.3 SIM Bus Clock Control and Generation
9.3.1 Bus Timing
9.3.2 Clock Startup from POR or LVI Reset
MC68HC708AS48
MOTOROLA
OSC1
—
PLL
CGMVCLK
Rev. 4.0
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in
from either an external oscillator or from the on-chip PLL.
(See
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. (See
When the power-on reset (POR) module or the low-voltage inhibit (LVI)
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after 4096 CGMXCLK cycles.
The RST pin is driven low by the SIM during this entire period. The bus
clocks start upon completion of the timeout.
MONITOR MODE
SELECT
CIRCUIT
CLOCK
USER MODE
BCS
Section 8. Clock Generator Module
CGM
Figure 9-3. CGM Clock Signals
PTC3
System Integration Module (SIM)
2
Section 8. Clock Generator Module
A
B S*
*When S = 1,
CGMOUT = B
CGMXCLK
CGMOUT
SIM Bus Clock Control and Generation
Figure
(CGM).)
System Integration Module (SIM)
9-3. This clock can come
SIM COUNTER
2
SIM
Advance Information
GENERATORS
BUS CLOCK
(CGM).)
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