MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 349
MC68HC708AS48
Manufacturer Part Number
MC68HC708AS48
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC68HC708AS48.pdf
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MC68HC708AS48
MOTOROLA
—
Rev. 4.0
Invalid Active Bit
Valid Active Logic 1
Valid Active Logic 0
PASSIVE
PASSIVE
PASSIVE
PASSIVE
In
beginning the next data bit (or symbol) occurs between the
passive-to-active transition beginning the current data bit (or symbol)
and a, the current bit would be invalid.
In
beginning the next data bit (or symbol) occurs between a and b, the
current bit would be considered a logic 1.
In
beginning the next data bit (or symbol) occurs between b and c, the
current bit would be considered a logic 0.
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Figure
Figure
Figure
Figure 20-10. J1850 VPW Received Active Symbol Times
Byte Data Link Controller–Digital (BDLC–D)
20-10(1), if the active-to-passive received transition
20-10(2), if the active-to-passive received transition
20-10(3), if the active-to-passive received transition
64 s
a
a
128 s
200 s
b
b
Byte Data Link Controller–Digital (BDLC–D)
c
c
d
(1) INVALID ACTIVE BIT
(2) VALID ACTIVE LOGIC 1
(3) VALID ACTIVE LOGIC 0
(4) VALID SOF SYMBOL
BDLC MUX Interface
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