MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 103

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

Freescale Semiconductor
Notes:
1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the
2. Recommend a weak pull-up resistor (2–10 k) be placed on this pin to OV
3. A valid clock must be provided at POR if TSEC4_TXD[2] is set = 1.
4. This pin is an open drain signal.
5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
6. Treat these pins as no connects (NC) unless using debug address functionality.
7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k pull-up or pull-down
8. The value of LALE, LGPL2, and LBCTL at reset set the e500 core clock to CCB clock PLL ratio. These pins require 4.7-k
9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
10.This pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit PCI
11.This output is actively driven during reset rather than being three-stated during reset.
12.These JTAG pins have weak internal pull-up P-FETs that are always enabled.
13.These pins are connected to the V
14.Internal thermally sensitive resistor.
15.No connections must be made to these pins if they are not used.
16.These pins are not connected for any use.
17.PCI specifications recommend that a weak pull-up resistor (2–10 k) be placed on the higher order pins to OV
19.If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state
20.This pin is only an output in FIFO mode when used as Rx flow control.
24.Do not connect.
local bus controller section, and is not mentioned in the DMA section even though the pin also functions as DMA_REQ2.
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kpull-down resistor. However, if
the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net
at reset, then a pullup or active driver is needed.
resistors. See
pull-up or pull-down resistors. See the
because it has other manufacturing test functions. This pin therefore is described as an I/O for boundary scan.
operation. Therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-bit
PCI device. See the PCI Specification.
and regulation.
64-bit buffer mode (pins PCI_AD[63:32] and PCI1_C_BE[7:4]).
during reset.
SD_IMP_CAL_RX
SD_IMP_CAL_TX
SD_PLL_TPA
SENSEVSS
MVREF
Signal
Section 20.2, “CCB/SYSCLK PLL Ratio.”
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Table 71. MPC8548E Pinout Listing (continued)
DD
/GND planes internally and may be used by the core power supply to improve tracking
Section 20.3, “e500 Core PLL Ratio.”
Package Pin Number
Analog Signals
AB26
M16
A18
U26
L28
DD
.
voltage signal
Reference
Pin Type
for DDR
—
O
I
I
I
MVREF
200 to
100 to
Supply
Package Description
Power
GND
GND
—
—
DD
when using
Notes
13
24
—
—
—
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