MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 68

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

High-Speed Serial Interfaces (HSSI)
68
•
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
— The input amplitude of the differential clock must be between 400 and 1600 mV differential
— For external DC-coupled connection, as described in
— For external AC-coupled connection, there is no common mode voltage requirement for the
Single-ended mode
— The reference clock can also be single-ended. The SD_REF_CLK input amplitude
— The SD_REF_CLK input average voltage must be between 200 and 400 mV.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC- or
Figure 40. Differential Reference Clock Input DC Requirements (External DC-Coupled)
peak-peak (or between 200 and 800 mV differential peak). In other words, each signal wire of
the differential pair must have a single-ended swing less than 800 mV and greater than 200 mV.
This requirement is the same for both external DC- or AC-coupled connection.
Receiver Characteristics,”
average voltage (common mode voltage) to be between 100 and 400 mV.
SerDes reference clock input requirement for DC-coupled connection scheme.
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above
the command mode voltage (SGND_SRDSn).
input requirement for AC-coupled connection scheme.
(single-ended swing) must be between 400 and 800 mV peak-to-peak (from V
SD_REF_CLK either left unconnected or tied to ground.
the SerDes reference clock input requirement for single-ended signaling mode.
AC-coupled externally. For the best noise performance, the reference of the clock could be DC-
or AC-coupled into the unused phase (SD_REF_CLK) through the same source impedance as
the clock input (SD_REF_CLK) in use.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
200 mV < Input Amplitude or Differential Peak < 800 mV
the maximum average current requirements sets the requirement for
Figure 41
Section 16.2.1, “SerDes Reference Clock
shows the SerDes reference clock
100 mV < V
Freescale Semiconductor
Figure 40
V
min
max
Figure 42
cm
V
to V
< 800 mV
< 400 mV
min
shows the
> 0 V
max
shows
) with