MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 54

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

JTAG
Figure 29
Figure 30
54
Valid times:
Output hold times:
JTAG external clock to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols used for timing specifications follow the pattern of t
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design.
The output timings are measured at the pins. All output timings assume a purely resistive 50-load (see
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
inputs and t
timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
going to the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
provides the AC test load for TDO and the boundary-scan outputs.
provides the JTAG clock input timing diagram.
(first two letters of functional block)(reference)(state)(signal)(state)
Table 44. JTAG AC Timing Specifications (Independent of SYSCLK)
External Clock
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Parameter
JTAG
Output
Figure 29. AC Test Load for the JTAG Interface
JTG
Figure 30. JTAG Clock Input Timing Diagram
Boundary-scan data
Boundary-scan data
Boundary-scan data
VM
clock reference (K) going to the high (H) state. Note that, in general, the clock reference
t
JTKHKL
VM = Midpoint Voltage (OV DD /2)
JTDXKH
TCLK
t
Z
JTG
TCLK
0
= 50 
.
VM
TDO
TDO
TDO
.
symbolizes JTAG timing (JT) with respect to the time data input signals
Symbol
t
t
t
t
t
t
JTKLOV
JTKLOX
JTKLDV
JTKLDX
JTKLDZ
JTKLOZ
(first two letters of functional block)(signal)(state)(reference)(state)
VM
for outputs. For example, t
2
R
L
= 50 
Min
TCLK
t
30
30
JTGR
4
2
3
3
to the midpoint of the signal in question.
OV
JTDVKH
DD
1
Max
t
JTGF
20
10
19
—
—
/2
9
(continued)
symbolizes JTAG device
Freescale Semiconductor
JTG
clock reference (K)
Unit
Figure
ns
ns
ns
29).
Notes
5, 6
5
5
for