MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 65

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MPC8543VTANGA

Manufacturer Part Number
MPC8543VTANGA
Description
Microprocessors - MPU PQ3 8543
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8543VTANGA

Product Category
Microprocessors - MPU
Rohs
yes
Processor Series
PowerQUICC III
Data Bus Width
32 bit
Maximum Clock Frequency
800 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
BGA
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
16 High-Speed Serial Interfaces (HSSI)
The device features one Serializer/Deserializer (SerDes) interface to be used for high-speed serial
interconnect applications. The SerDes interface can be used for PCI Express and/or serial RapidIO data
transfers.
This section describes the common portion of SerDes DC electrical specifications, which is the DC
requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits
are also shown.
16.1
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms
used in the description and specification of differential signals.
Figure 38
description. The figure shows a waveform for either a transmitter output (SD_TX and SD_TX) or a
receiver input (SD_RX and SD_RX). Each signal swings between A volts and B volts where A > B.
Using this waveform, the definitions are as follows. To simplify the illustration, the following definitions
assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling
environment.
Freescale Semiconductor
Single-ended swing
The transmitter output signals and the receiver input signals SD_TX, SD_TX, SD_RX and SD_RX
each have a peak-to-peak swing of A – B volts. This is also referred as each signal wire’s
single-ended swing.
Differential output voltage, V
The differential output voltage (or swing) of the transmitter, V
the two complimentary output voltages: V
or negative.
Differential input voltage, V
The differential input voltage (or swing) of the receiver, V
complimentary input voltages: V
negative.
Differential peak voltage, V
The peak value of the differential transmitter output signal or the differential receiver input signal
is defined as differential peak voltage, V
Differential peak-to-peak, V
Because the differential output signal of the transmitter and the differential input signal of the
receiver each range from A – B to –(A – B) volts, the peak-to-peak value of the differential
transmitter output signal or the differential receiver input signal is defined as differential
peak-to-peak voltage, V
swing in amplitude, or twice of the differential peak. For example, the output differential
peak-to-peak voltage can also be calculated as V
Common mode voltage, V
The common mode voltage is equal to one half of the sum of the voltages between each conductor
Signal Terms Definition
shows how the signals are defined. For illustration purpose, only one SerDes lane is used for the
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
DIFFp-p
cm
DIFFp
ID
DIFFp-p
OD
(or differential input swing):
= 2  V
SD_RX
(or differential output swing):
DIFFp
– V
DIFFp
SD_TX
SD_RX
= 2  |(A – B)| volts, which is twice of differential
= |A – B| volts.
TX-DIFFp-p
– V
. The V
SD_TX
ID
ID
. The V
, is defined as the difference of the two
= 2 |V
value can be either positive or
OD
, is defined as the difference of
OD
OD
High-Speed Serial Interfaces (HSSI)
value can be either positive
|.
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