MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 150

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

Document Revision History
150
Number
Rev.
2
1
0
04/2008
10/2007
07/2007
Date
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
• Removed 1:1 support on
• Removed MDM from
•
•
• Split
• Adjusted maximum SYSCLK frequency down in
• Clarified notes to
• Added
• Clarified descriptions and added PCI/PCI-X to
• Removed support for 266 and 200 Mbps data rates per device erratum GEN-13 in
• Clarified Note 4 of
• Clarified the reference clock used in
• Corrected V
• Corrected V
• Removed DC parameters from
• Corrected V
• Corrected t
• Updated parameter descriptions for t
• Updated parameter descriptions for t
• Added LUPWAIT signal to
• Added LGTA signal to
• Corrected LUPWAIT assertion in
• Clarified the PCI reference clock in
• Added
• Added PBGA thermal information in
• Updated.”
• Updated
• Initial Release
Figure 57, “PLL Power Supply Filter Circuit with PLAT
Figure 58, “PLL Power Supply Filter Circuit with CORE
Supply Filter Circuit”) into three figures: the original (now specific for AVDD_PCI/AVDD_LBIU) and two
new ones.
device erratum GEN-13.
DDR2
Characteristics.”
Table
Timing Parameters (BV
(BV
Timing Parameters—PLL
and t
Signals (PLL Bypass
FC-PBGA with Full Lid and Version 3.1.x Silicon with Stamped
DD
Figure 59, “PLL Power Supply Filter Circuit with PCI/LBIU
LBIXKH2
34, and
SDRAM.”
= 2.5 V)—PLL
Section 4.4, “PCI/PCI-X Reference Clock
Section 17.1, “Package
Table 88. Document Revision History (continued)
Table 87, “Part Numbering
MDC
IH
IL
IH
.
(max) in
(min) in
(min) in
Table
(min) in
Table 6, “EC_GTX_CLK125 AC Timing
Table 19, “DDR SDRAM Output AC Timing
35.
Mode).”
Table 18, “DDR SDRAM Input AC Timing
Enabled.”
Table 22, “GMII, MII, RMII, and TBI DC Electrical
Table 36, “MII Management DC Electrical
Table 23, “GMII, MII, RMII, TBI, RGMII, RTBI, and FIFO DC Electrical
Figure
Table 37, “MII Management AC Timing
DD
Table 82, “e500 Core to CCB Clock
Bypassed.” Note that t
= 3.3 V)—PLL
Figure 23, “Local Bus Signals (PLL
25,
Parameters.”
Table
Figure
Figure 26
Section 15.2, “PCI/PCI-X AC Electrical
Nomenclature.”
Section 21.2, “Thermal for Version 2.1.1, 2.1.2, and 2.1.3 Silicon
Section 7.2, “DUART AC Electrical
LBIVKH1
LBIVKH1
Substantive Change(s)
24,
26,
Table
Enabled” and
and
, t
, t
Figure 27
LBIVKH2
LBIVKL2
Table 9, “PLL Lock
25,
LBIVKL2
Figure
Table 5, “SYSCLK AC Timing
Timing.”
Table
, t
, t
Pins” (AVDD_PLAT).
and
LBIXKH1
28.
Pins” (AVDD_CORE).
LBIXKH1
Table 40, “Local Bus Timing Parameters
and t
Specifications.”
26,
Figure
LBIXKL2
Table
Ratio.”
Specifications.”
Pins,” (formerly called just “PLL Power
, and t
Enabled)” and
Specifications.”
, and t
Lid.”
Specifications.” MDM is an Output.
Characteristics.”
28.
Times.”
27,
were previously labeled t
LBIXKL2
LBIXKH2
Table
Characteristics.”
Specifications.”
Specifications”
Freescale Semiconductor
in
28,
in
Figure 24, “Local Bus
Specifications” per
Table 42, “Local Bus
Table 40, “Local Bus
Section 6, “DDR and
Table
29,
Table
LBIVKH2
32,