MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 2

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

Overview
1.1
The following list provides an overview of the device feature set:
2
MII, GMII, TBI,
MII, GMII, TBI,
MII, GMII, TBI,
SDRAM
SDRAM
•
RTBI, RGMII,
RTBI, RGMII,
RTBI, RGMII,
RTBI, RGMII,
Flash
GPIO
IRQs
DDR
Serial
High-performance 32-bit core built on Power Architecture® technology.
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can
— Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive
— Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)
— 36-bit real addressing
— Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set
— Memory management unit (MMU). Especially designed for embedded applications. Supports
— Enhanced hardware and software debug support
I
I
Key Features
2
2
C
C
be locked entirely or on a per-line basis, with separate locking for instructions and data.
instruction set for vector (64-bit) integer and fractional operations. These instructions use both
the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU.
floating-point instructions that use the 64-bit GPRs.
for single-precision (32-bit) floating-point instructions.
4-Kbyte to 4-Gbyte page sizes.
RMII
RMII
RMII
RMII
Programmable Interrupt
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Local Bus Controller
Memory Controller
Controller (PIC)
DDR/DDR2/
Controller
Controller
10/100/1Gb
10/100/1Gb
10/100/1Gb
10/100/1Gb
DUART
eTSEC
eTSEC
eTSEC
eTSEC
I
I
2
2
C
C
Figure 1. Device Block Diagram
Coherency
Security
OceaN
Module
Switch
Fabric
Engine
Engine
e500
XOR
Core Complex
512-Kbyte
L2 Cache/
SRAM
32-bit PCI Bus Interface
Bus
(If 64-bit not used)
64-bit PCI/PCI-X
4-Channel DMA
Serial RapidIO
Bus Interface
PCI Express
32-bit PCI/
Controller
or
32-Kbyte L1
Instruction
Cache
e500 Core
Freescale Semiconductor
32-Kbyte
L1 Data
Cache
4x RapidIO
x8 PCI Express
PCI 32-bit
66 MHz
PCI/PCI-X
133 MHz