MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 133

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MPC8543VTANGA

Manufacturer Part Number
MPC8543VTANGA
Description
Microprocessors - MPU PQ3 8543
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8543VTANGA

Product Category
Microprocessors - MPU
Rohs
yes
Processor Series
PowerQUICC III
Data Bus Width
32 bit
Maximum Clock Frequency
800 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
BGA
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
20.3
This table describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock.
This ratio is determined by the binary value of LBCTL, LALE, and LGPL2 at power up, as shown in this
table.
20.4
Table
clock to SYSCLK ratio in comparison to the memory bus clock speed.
Freescale Semiconductor
Note: Due to errata Gen 13 the max sys clk frequency must not exceed 100 MHz if the core clk frequency is below
1200 MHz.
LBCTL, LALE, LGPL2
SYSCLK Ratio
83This table shows the expected frequency values for the platform frequency when using a CCB
Binary Value of
CCB to
e500 Core PLL Ratio
Frequency Options
10
12
16
20
2
3
4
5
6
8
9
Signals
000
001
010
011
Table 83. Frequency Options of SYSCLK with Respect to Memory Bus Speeds
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
16.66
333
e500 core:CCB Clock Ratio
400
500
25
Table 82. e500 Core to CCB Clock Ratio
Reserved
4:1
9:2
3:2
33.33
333
400
533
Platform/CCB Frequency (MHz)
41.66
333
375
417
500
SYSCLK (MHz)
LBCTL, LALE, LGPL2
66.66
Binary Value of
333
400
533
Signals
100
101
110
111
333
415
500
83
100
400
500
e500 core:CCB Clock Ratio
111
333
445
2:1
5:2
3:1
7:2
133.33
400
533
Clocking
133

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