MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 8

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

Overview
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— Memory prefetching of PCI read accesses
— Supports posting of processor-to-PCI and PCI-to-memory writes
— PCI 3.3-V compatible
— Selectable hardware-enforced coherency
Serial RapidIO™ interface unit
— Supports RapidIO™ Interconnect Specification, Revision 1.2
— Both 1× and 4× LP-serial link interfaces
— Long- and short-haul electricals with selectable pre-compensation
— Transmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbps) per lane
— Auto detection of 1- and 4-mode operation during port initialization
— Link initialization and synchronization
— Large and small size transport information field support selectable at initialization time
— 34-bit addressing
— Up to 256 bytes data payload
— All transaction flows and priorities
— Atomic set/clr/inc/dec for read-modify-write operations
— Generation of IO_READ_HOME and FLUSH with data for accessing cache-coherent data at
— Receiver-controlled flow control
— Error detection, recovery, and time-out for packets and control symbols as required by the
— Register and register bit extensions as described in part VIII (Error Management) of the
— Hardware recovery only
— Register support is not required for software-mediated error recovery.
— Accept-all mode of operation for fail-over support
— Support for RapidIO error injection
— Internal LP-serial and application interface-level loopback modes
— Memory and PHY BIST for at-speed production test
RapidIO-compatible message unit
— 4 Kbytes of payload per message
— Up to sixteen 256-byte segments per message
— Two inbound data message structures within the inbox
— Capable of receiving three letters at any mailbox
— Two outbound data message structures within the outbox
— Capable of sending three letters simultaneously
— Single segment multicast to up to 32 devIDs
— Chaining and direct modes in the outbox
a remote memory system
RapidIO specification
RapidIO specification
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor