MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 22

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

DDR and DDR2 SDRAM
6.2
This section provides the AC electrical characteristics for the DDR SDRAM interface. The DDR
controller supports both DDR1 and DDR2 memories. DDR1 is supported with the following AC timings
at data rates of 333 MHz. DDR2 is supported with the following AC timings at data rates down to
333 MHz.
6.2.1
This table provides the input AC timing specifications for the DDR SDRAM when GV
Table 17
This table provides the input AC timing specifications for the DDR SDRAM interface.
22
At recommended operating conditions
At recommended operating conditions.
At recommended operating conditions.
AC input low voltage
AC input high voltage
AC input low voltage
AC input high voltage
Controller Skew for MDQS—MDQ/MECC
Notes:
1. t
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t
is captured with MDQS[n]. This must be subtracted from the total timing budget.
determined by the following equation: t
absolute value of t
CISKEW
provides the input AC timing specifications for the DDR SDRAM when GV
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
DDR SDRAM AC Electrical Characteristics
DDR SDRAM Input AC Timing Specifications
Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
Parameter
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Table 17. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
CISKEW
Parameter
Parameter
.
Table 18. DDR SDRAM Input AC Timing Specifications
533 MHz
400 MHz
333 MHz
DISKEW
= ± (T/4 – abs(t
Symbol
t
CISKEW
CISKEW
Symbol
Symbol
V
V
V
V
IH
IH
IL
IL
)) where T is the clock period and abs(t
–300
–365
–390
Min
MV
MV
REF
REF
Min
Min
—
—
+ 0.25
+ 0.31
Max
300
365
390
DISKEW
MV
MV
Freescale Semiconductor
REF
REF
DD
Max
Max
DD
—
—
. This can be
(typ) = 2.5 V.
– 0.25
– 0.31
Unit
(typ) = 1.8 V.
ps
CISKEW
Notes
) is the
Unit
Unit
1, 2
V
V
V
V