MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 70

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MPC8543VTANGA

Manufacturer Part Number
MPC8543VTANGA
Description
Microprocessors - MPU PQ3 8543
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8543VTANGA

Product Category
Microprocessors - MPU
Rohs
yes
Processor Series
PowerQUICC III
Data Bus Width
32 bit
Maximum Clock Frequency
800 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
BGA
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
High-Speed Serial Interfaces (HSSI)
Figure 43
assumes that the DC levels of the clock driver chip is compatible with SerDes reference clock input’s DC
requirement.
Figure 44
Since LVDS clock driver’s common mode voltage is higher than the SerDes reference clock input’s
allowed range (100–400 mV), AC-coupled connection scheme must be used. It assumes the LVDS output
driver features 50-termination resistor. It also assumes that the LVDS transmitter establishes its own
common mode level without relying on the receiver or other external component.
Figure 45
Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with
the SerDes reference clock input’s DC requirement, AC-coupling must be used.
the LVPECL clock driver’s output impedance is 50 R1 is used to DC-bias the LVPECL outputs prior
70
LVDS CLK Driver Chip
HCSL CLK Driver Chip
Total 50 Assume clock driver’s
output impedance is about 16 
Clock Driver
Clock Driver
Clock Driver
Clock Driver
Figure 43. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
Figure 44. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It
shows the SerDes reference clock connection reference circuits for LVDS type clock driver.
shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.
CLK_Out
CLK_Out
CLK_Out
CLK_Out
CLK_Out
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
33 
33 
10 nF
10 nF
100 Differential PWB Trace
Clock driver vendor dependent
source termination resistor
100 Differential PWB Trace
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
50 
50 
50 
50 
Figure 45
Freescale Semiconductor
SerDes Refer.
CLK Receiver
SerDes Refer.
CLK Receiver
MPC8548E
MPC8548E
assumes that

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