MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 67

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

16.2.2
The DC level requirement for the SerDes reference clock inputs is different depending on the signaling
mode used to connect the clock driver chip and SerDes reference clock inputs as described below:
Freescale Semiconductor
•
•
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— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. See the differential
The maximum average current requirement that also determines the common mode voltage range:
— When the SerDes reference clock differential inputs are DC coupled externally with the clock
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V
— If the device driving the SD_REF_CLK and SD_REF_CLK inputs cannot drive 50  to
The input amplitude requirement:
— This requirement is described in detail in the following sections.
Differential mode
in
termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.
mode and single-ended mode description below for further detailed requirements.
driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the
exact common mode input voltage is not critical as long as it is within the range allowed by the
maximum average current of 8 mA (see the following bullet for more detail), since the input is
AC-coupled on-chip.
(0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above
SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by
a clock driver with output driven by its current source from 0 to 16 mA (0–0.8 V), such that
each phase of the differential input has a single-ended swing from 0 V to 800 mV with the
common mode voltage at 400 mV.
SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations, then it
must be AC-coupled off-chip.
DC Level Requirement for SerDes Reference Clocks
Figure
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
39. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-
Figure 39. Receiver of SerDes Reference Clocks
SD_REF_CLK
SD_REF_CLK
50 
50 
Input
Amp
High-Speed Serial Interfaces (HSSI)
67