MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 33

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

Figure 11
8.2.3.2
This table provides the MII receive AC timing specifications.
Figure 12
Freescale Semiconductor
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise (20%–80%)
RX_CLK clock fall time (80%–20%)
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. Guaranteed by design.
inputs and t
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
going to the high (H) state or setup time. Also, t
signals (D) went invalid (X) relative to the t
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of t
with the appropriate letter: R (rise) or F (fall).
shows the MII transmit AC timing diagram.
provides the AC test load for eTSEC.
(first two letters of functional block)(reference)(state)(signal)(state)
MII Receive AC Timing Specifications
TXD[3:0]
TX_CLK
Parameter/Condition
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
TX_EN
TX_ER
Output
MRX
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
Table 29. MII Receive AC Timing Specifications
Figure 11. MII Transmit AC Timing Diagram
t
MTXH
MRX
Figure 12. eTSEC AC Test Load
t
MTX
clock reference (K) going to the low (L) state or hold time. Note that, in general,
MRDXKL
Z
0
= 50 
symbolizes MII receive timing (GR) with respect to the time data input
t
t
MTKHDX
t
MRXH
Symbol
MTXF
t
t
MRDVKH
MRDXKH
t
t
t
MRXR
MRXF
(first two letters of functional block)(signal)(state)(reference)(state)
t
MRX
MRX
for outputs. For example, t
/t
MRX
2
2
2
1
R
L
t
MTXR
= 50 
10.0
10.0
Min
1.0
1.0
35
—
—
Enhanced Three-Speed Ethernet (eTSEC)
LV
DD
MRDVKH
Typ
400
40
—
—
—
—
—
/2
MRX
symbolizes MII receive
clock reference (K)
Max
4.0
4.0
65
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
%
for
33