MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 136

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

System Design Information
level must always be equivalent to V
through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits per PLL power supply as illustrated in
AV
one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It must be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit must be placed as close as possible to the specific AV
coupled from nearby circuits. It must be routed directly from the capacitors to the AV
the periphery of the footprint, without the inductance of vias.
Figure 57
The AV
the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in
following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the
AV
the AV
and finally the 1  resistor to the board supply plane. The capacitors are connected from AV
136
DD
DD
_SRDS ball to ensure it filters out as much noise as possible. The ground connection must be near
pins. By providing independent filters to each PLL the opportunity to cause noise injection from
DD
DD
_SRDS ball. The 0.003-µF capacitor is closest to the ball, followed by the two 2.2 µF capacitors,
through
_SRDS signal provides power for the analog portions of the SerDes PLL. To ensure stability of
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Figure 59
V
V
V
DD
DD
DD
Figure 59. PLL Power Supply Filter Circuit with PCI/LBIU Pins
Figure 58. PLL Power Supply Filter Circuit with CORE Pins
Figure 57. PLL Power Supply Filter Circuit with PLAT Pins
shows the PLL power supply filter circuits.
150
180
10
DD
, and preferably these voltages are derived directly from V
2.2 µF
2.2 µF
2.2 µF
GND
GND
GND
Low ESL Surface Mount Capacitors
Low ESL Surface Mount Capacitors
Low ESL Surface Mount Capacitors
2.2 µF
2.2 µF
2.2 µF
DD
AV
AV
AV
pin being supplied to minimize noise
DD
DD
DD
_PLAT
_CORE
_PCI/AV
Figure
DD
57, one to each of the
_LBIU
Freescale Semiconductor
DD
pin, which is on
DD
_SRDS to
DD