MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 42

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

At recommended operating conditions with OV
Ethernet Management Interface Electrical Characteristics
Figure 21
42
MDC fall time
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (f
3.The maximum ECn_MDC output clock frequency is defined based on the maximum platform frequency for device (533 MHz)
4. Guaranteed by design.
5. t
inputs and t
data timing (MD) for the time t
Also, t
(V) relative to the t
is used with the appropriate letter: R (rise) or F (fall).
ECn_MDC output clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of
device’s MIIMCFG register, based on the platform (CCB) clock running for the device. The formula is: Platform Frequency
(CCB)  (2 × Frequency Divider determined by MIICFG[MgmtClk] encoding selection). For example, if
MIICFG[MgmtClk] = 000 and the platform (CCB) is currently running at 533 MHz, f
8.3 MHz. That is, for a system running at a particular platform frequency (f
programmed between maximum f
Configuration Register (MIIMCFG),” in the MPC8548E PowerQUICC™ III Integrated Processor Family Reference Manual for
more detail.
divided by 64, while the minimum ECn_MDC output clock frequency is defined based on the minimum platform frequency for
device (333 MHz) divided by 448, following the formula described in Note 2 above.
CCB
is the platform (CCB) clock period.
MDDVKH
shows the MII management AC timing diagram.
Parameter
(first two letters of functional block)(reference)(state)(signal)(state)
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
(Output)
MDC
(Input)
MDIO
MDIO
MDC
Table 37. MII Management AC Timing Specifications (continued)
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention
Figure 21. MII Management Interface Timing Diagram
MDC
MDC
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
t
MDCH
= f
DD
Symbol
t
t
CCB
MDHF
MDDVKH
is 3.3 V ± 5%.
t
MDC
 64 and minimum f
t
1
MDKHDX
Min
—
t
MDCF
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
MDC
= f
t
MDDXKH
CCB
CCB
Typ
t
MDCR
), the ECn_MDC output clock frequency can be
 448. See 14.5.3.6.6, “MII Management
MDC
= 533)  (2 × 4 × 8) = 533)  64 =
MDKHDX
Max
10
symbolizes management
Freescale Semiconductor
CCB
Unit
ns
). The actual
Notes
for
4