MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 16

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

Input Clocks
4
This section discusses the timing for the input clocks.
4.1
The following table provides the system clock (SYSCLK) AC timing specifications for the device.
4.2
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then
used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter
specification. The minimum pulse width of the RTC signal must be greater than 2x the period of the CCB
clock. That is, minimum clock high time is 2  t
no minimum RTC frequency; RTC may be grounded if not needed.
16
At recommended operating conditions (see
SYSCLK frequency
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle
SYSCLK jitter
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYSCLK driver’s closed loop jitter bandwidth must be <500 kHz at –20 dB. The bandwidth must be set low to allow
6. This parameter has been adjusted slower according to the workaround for device erratum GEN 13.
7. For spread spectrum clocking. Guidelines are + 0% to –1% down spread at modulation rate between 20 and 60 kHz on
8. System with operating core frequency less than 1200 MHz must limit SYSCLK frequency to 100 MHz maximum.
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies.See
settings.
cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.
SYSCLK.
Input Clocks
System Clock Timing
Real Time Clock Timing
Parameter/Condition
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Section 20.2, “CCB/SYSCLK PLL Ratio,”
Table 5. SYSCLK AC Timing Specifications
Table
2) with OV
t
KHK
Symbol
f
t
t
SYSCLK
SYSCLK
KH
/t
—
SYSCLK
, t
CCB
KL
DD
, and minimum clock low time is 2  t
= 3.3 V ± 165 mV
Min
7.5
0.6
16
40
—
and
Section 20.3, “e500 Core PLL Ratio,”
.
Typ
1.0
—
—
—
—
±150
Max
133
1.2
60
60
Freescale Semiconductor
MHz
Unit
CCB
ns
ns
ps
%
. There is
for ratio
1, 6, 7,
6, 7,
Notes
4,
2
3
5
8
8