MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 12

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

Electrical Characteristics
The following figure shows the undershoot and overshoot voltages at the interfaces of this device.
The core voltage must always be provided at nominal 1.1 V. Voltage to the processor interface I/Os are
provided through separate sets of supply pins and must be provided at the voltages shown in
input voltage threshold scales with respect to the associated I/O supply voltage. OV
receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR
SDRAM interface uses a single-ended differential receiver referenced the externally supplied MV
signal (nominally set to GV
12
Junction temperature range
Notes:
1. This voltage is the input to the filter discussed in
2. Caution: MV
3. Caution: OV
4. Caution: L/TV
at the AV
power-on reset and power-down sequences.
power-on reset and power-down sequences.
power-on reset and power-down sequences.
DD
pin, which may be reduced from V
IN
IN
V
IN
IH
Figure 2. Overshoot/Undershoot Voltage for GV
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
must not exceed OV
must not exceed GV
must not exceed L/TV
Notes:
1. t
2. Note that with the PCI overshoot allowed (as specified above), the device
For I
For DDR, t
For eTSEC, t
For LBIU, t
For PCI, t
For SerDes, t
does not fully comply with the maximum AC ratings and device protection
guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3).
CLOCK
B/G/L/O/TV
B/G/L/O/TV
V
Table 2. Recommended Operating Conditions (continued)
Characteristic
IL
2
C and JTAG, t
refers to the clock period associated with the respective interface:
DD
B/G/L/O/TV
CLOCK
GND – 0.3 V
GND – 0.7 V
CLOCK
CLOCK
/2) as is appropriate for the SSTL2 electrical signaling standard.
DD
CLOCK
CLOCK
DD
DD
DD
+ 20%
references PCIn_CLK or SYSCLK.
+ 5%
GND
references MCLK.
references LCLK.
DD
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
CLOCK
DD
references EC_GTX_CLK125.
references SD_REF_CLK.
by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
DD
references SYSCLK.
Section 22.2, “PLL Power Supply Filtering,”
by the filter.
Not to Exceed 10%
of t
CLOCK
DD
Symbol
/OV
Tj
1
DD
/LV
Recommended
DD
/BV
0 to 105
Value
and not necessarily the voltage
DD
/TV
DD
Freescale Semiconductor
DD
and LV
Unit
Table
C
DD
REF
based
2. The
Notes
—