MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 131

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

Freescale Semiconductor
e500 core processor frequency
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.
Memory bus clock speed
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.
Memory bus clock speed
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
2. The memory bus speed is half of the DDR/DDR2 data rate, hence, half of the platform clock frequency.
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. See
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. See
settings.
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. See
settings.
Characteristic
Table 78. Memory Bus Clocking Specifications (MPC8548E and MPC8547E)
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Section 20.2, “CCB/SYSCLK PLL Ratio,”
Characteristic
Characteristic
Table 77. Processor Core Clocking Specifications (MPC8543E)
Table 79. Memory Bus Clocking Specifications (MPC8545E)
Section 20.2, “CCB/SYSCLK PLL Ratio,”
Section 20.2, “CCB/SYSCLK PLL Ratio,”
Min
800
Maximum Processor Core Frequency
800 MHz
and
Maximum Processor Core Frequency
Maximum Processor Core Frequency
Section 20.3, “e500 Core PLL Ratio,”
Max
800
Min
Min
166
166
1000, 1200, 1333 MHz
and
and
800, 1000, 1200 MHz
Section 20.3, “e500 Core PLL Ratio,”
Section 20.3, “e500 Core PLL Ratio,”
Min
800
1000 MHz
Max
Max
266
200
1000
Max
for ratio settings.
MHz
MHz
MHz
Unit
Unit
Unit
for ratio
for ratio
Notes
Notes
Notes
Clocking
1, 2
1, 2
1, 2
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