MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 72

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

High-Speed Serial Interfaces (HSSI)
16.2.4
The clock driver selected must provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver must be 50  to match the
transmission line and reduce reflections which are a source of noise to the system.
The detailed AC requirements of the SerDes reference clocks are defined by each interface protocol based
on application usage. See the following sections for detailed information:
16.2.4.1
SD_REF_CLK/SD_REF_CLK are designed to work with a spread spectrum clock (+0% to –0.5%
spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better results,
a source without significant unintended modulation must be used.
16.3
Figure 47
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below
(PCI Express, Serial Rapid IO, or SGMII) in this document based on the application usage:
Note that external an AC coupling capacitor is required for the above three serial transmission protocols
with the capacitor value defined in the specification of each protocol section.
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Section 17.2, “AC Requirements for PCI Express SerDes Clocks”
Section 18.2, “AC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK”
Section 17, “PCI Express”
Section 18, “Serial RapidIO”
SerDes Transmitter and Receiver Reference Circuits
shows the reference circuits for SerDes data lane’s transmitter and receiver.
AC Requirements for SerDes Reference Clocks
Spread Spectrum Clock
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Transmitter
Figure 47. SerDes Transmitter and Receiver Reference Circuits
50 
50 
SD_TXn
SD_TXn
SD_RXn
SD_RXn
50 
50 
Receiver
Freescale Semiconductor