MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 24

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

DDR and DDR2 SDRAM
Figure 3
24
At recommended operating conditions.
MDQS epilogue end
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that t
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
(A) are setup (S) or output valid time. Also, t
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay
as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these 2 parameters
have been set to the same adjustment value. See the MPC8548E PowerQUICC III Integrated Processor Reference Manual
for a description and understanding of the timing modifications enabled by use of these bits.
(MECC), or data mask (MDM). The data strobe must be centered inside of the data eye at the pins of the microprocessor.
symbol conventions described in note 1.
DDKHAS
shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t
symbolizes DDR timing (DD) for the time t
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
For the ADDR/CMD setup and hold specifications in
assumed that the clock control register is set to adjust the memory clocks by
1/2 applied cycle.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
follows the symbol conventions described in note 1. For example, t
Table 19. DDR SDRAM Output AC Timing Specifications (continued)
MCK[n]
MCK[n]
MDQS
MDQS
Figure 3. Timing Diagram for tDDKHMH
DDKLDX
Symbol
t
DDKHME
MCK
symbolizes DDR timing (DD) for the time t
t
DDKHMH(min)
t
memory clock reference (K) goes from the high (H) state until outputs
DDKHMHmax)
1
t
MCK
NOTE
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. Output hold time can be read as DDR timing
= –0.6 ns
–0.6
= 0.6 ns
Min
Table
DDKHMH
DDKHMH
19, it is
Max
0.6
can be modified through control
describes the DDR timing (DD)
MCK
Freescale Semiconductor
memory clock reference
DDKHMP
Unit
ns
follows the
DDKHMH
Notes
6
for
).