MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 130

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MPC8543VTANGA

Manufacturer Part Number
MPC8543VTANGA
Description
Microprocessors - MPU PQ3 8543
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8543VTANGA

Product Category
Microprocessors - MPU
Rohs
yes
Processor Series
PowerQUICC III
Data Bus Width
32 bit
Maximum Clock Frequency
800 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
BGA
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
Clocking
20 Clocking
This section describes the PLL configuration of the device. Note that the platform clock is identical to the
core complex bus (CCB) clock.
20.1
Table 75
through
130
e500 core processor frequency
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.
e500 core processor frequency
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. See
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. See
Table 80
through
Clock Ranges
Table 75. Processor Core Clocking Specifications (MPC8548E and MPC8547E)
Characteristic
Characteristic
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Section 20.2, “CCB/SYSCLK PLL Ratio,”
Section 20.2, “CCB/SYSCLK PLL Ratio,”
Table 77
provide the clocking specifications for the memory bus.
Table 76. Processor Core Clocking Specifications (MPC8545E)
provide the clocking specifications for the processor cores and
Min
800
Min
800
1000 MHz
800 MHz
Maximum Processor Core Frequency
Maximum Processor Core Frequency
1000
Max
Max
and
800
and
Section 20.3, “e500 Core PLL Ratio,”
Section 20.3, “e500 Core PLL Ratio,”
Min
800
Min
800
1200 MHz
1000 MHz
1200
1000
Max
Max
Min
800
Min
800
1333 MHz
1200 MHz
1333
1200
Max
Max
Freescale Semiconductor
for ratio settings.
for ratio settings.
MHz
MHz
Unit
Unit
Table
78,
Notes
Notes
1, 2
1, 2

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