MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 149

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

Freescale Semiconductor
Number
Rev.
4
3
04/2009
01/2009
Date
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
• In
• In
• In
• Modified
• Modified DDR clk rate min from 133 to 166 MHz.
• Modified note in
• In
• In
• Modified
• Added a note on
• In
• Added note to
•
• In
•
•
• In
• In
• In
• In
• In
• In
• In
• In
• In
• Added new section,
•
•
• Added information to
•
•
moved text, “MII management voltage” from LV
OVDD row of input voltage section.
time.
OV
column, and changed all instances of “LO” to “L0.” Also added note 8.
and in note 3, changed “TRX-EYE-MEDIAN-to-MAX-JITTER,” to “T
frequency is less than 1200 MHz
Pinout
[Section 4.6, “Platform Frequency Requirements for PCI-Express and Serial RapidIO.”
minimum frequency equation to be 527 MHz for PCI x8.
Section 4.5, “Platform to FIFO Restrictions.”
Section 8.1, “Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI/RMII Electrical Characteristics.”
and add ‘or 2.5 V’ after 3.3 V.
TSECn_TX_CLK.
high from 32 to 48 ns.
Section 16.1, “DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK.”
paragraph.
Section 17.1, “DC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK.”
paragraph.
Section 22.3, “Decoupling Recommendations.”
Table 87, “Part Numbering Nomenclature.”
Table 57,
Table
Table
Table
Table 56,
Table 71,
Table
Table
Table 24
Table
Table
Table 30
Section 8.2.5, “TBI Single-Clock Mode AC Specifications.”
Table
Table
Table
DD
.
ListingTable 74,
5, “SYSCLK AC Timing Specifications,” added notes 7 and 8 to SYSCLK frequency and cycle
1, “Absolute Maximum Ratings
36, “MII Management DC Electrical Characteristics,” changed all instances of LV
5, added note 7.
23, modified table title to include GMII, MII, RMII, and TBI.
25, added a note.
26,
34,
36, changed all instances of OV
37, “MII Management AC Timing Specifications,” changed MDC minimum clock pulse width
Table 88. Document Revision History (continued)
Section 16, “High-Speed Serial Interfaces
Table
and
and
“Differential Receiver (RX) Input Specifications,” modified equations in Comments column,
“Differential Transmitter (TX) Output Specifications,” modified equations in Comments
“MPC8548E Pinout
Table
Table
Table
83, “Frequency Options of SYSCLK with Respect to Memory Bus Speeds.”
Table
Figure
Table
Section 4.1, “System Clock
27,
35,
Section 16, “High-Speed Serial Interfaces (HSSI).”
83, “Frequency Options of SYSCLK with Respect to Memory Bus Speeds.”
Figure
25, changed clock period minimum to 5.3.
Table
Figure
75, “Processor Core Clocking Specifications (MPC8548E and MPC8547E), “.”
15, changed all instances of PMA to TSECn.
“MPC8543E Pinout Listing,” added note 5 to LA[28:31].
28,
63, both in figure and in note.
18, and
Table
ListingTable 72,
Substantive Change(s)
Figure
29, and
1
DD
,” and in
In Silicon Version column added Ver. 2.1.2.
to LV
20, changed all instances of REF_CLK to
Changed platform clock frequency to 4.2.
Timing,” to limit the SYSCLK to 100 MHz if the core
Table
DD
Modified the recommendation.
“MPC8547E Pinout
DD
Table
/TV
(HSSI),” to reflect that there is only one SerDes.
/TV
30, removed subtitle from table title.
DD
DD
2, “Recommended Operating Conditions,”
to OV
.
Replaced first paragraph.
DD
, added “Ethernet management” to
RX-EYE-MEDIAN-to-MAX-JITTER
ListingTable 73,
Document Revision History
Added MII after GMII
“MPC8545E
Added new
Changed
Added new
DD
/OV
.”
DD
149
to