MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 57

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

Figure 33
Freescale Semiconductor
Noise margin at the LOW level for each connected device
(including hysteresis)
Noise margin at the HIGH level for each connected
device (including hysteresis)
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. As a transmitter, the device provides a delay time of at least 300 ns for the SDA signal (see the V
3. The maximum t
4. Guaranteed by design.
inputs and t
with respect to the time data input signals (D) reach the valid state (V) relative to the t
(H) state or setup time. Also, t
(S) went invalid (X) relative to the t
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition. When the
device acts as the I
SDA are balanced, the device would not cause unintended generation of Start or Stop condition. Therefore, the 300 ns SDA
output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the device
as a transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure both the desired
I
kHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default setting of 0x10 (decimal 16):
I
FDR bit setting
Actual FDR divider selected
Actual I
For the detail of I
I
2
2
2
C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I
C source clock frequency
C source clock frequency is half of the CCB clock frequency for the device.
2
C SCL frequency generated
provides the AC test load for the I
(first two letters of functional block)(reference)(state)(signal)(state)
I2DXKL
2
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
C frequency calculation, see Determining the I
2
Parameter
C bus master while transmitting, the device drives both SCL and SDA. As long as the load on SCL and
has only to be met if the device does not stretch the LOW period (t
Output
Table 46. I
I2SXKL
I2C
symbolizes I
clock reference (K) going to the low (L) state or hold time. Also, t
371 kHz
333 MHz
0x2A
896
2
C AC Electrical Specifications (continued)
Figure 33. I
Z
0
2
= 50 
2
C timing (I2) for the time that the data with respect to the start condition
C.
266 MHz
0x05
704
378 kHz
2
Symbol
C AC Test Load
V
V
NH
NL
2
(first two letters of functional block)(signal)(state)(reference)(state)
C Frequency Divider Ratio for SCL (AN2919). Note that the
for outputs. For example, t
200 MHz
390 kHz
0x26
512
1
0.1  OV
0.2  OV
R
L
Min
= 50 
346 kHz
133 MHz
0x00
384
DD
DD
I2C
clock reference (K) going to the high
OV
I2CL
I2DVKH
DD
Max
2
—
—
) of the SCL signal.
C SCL clock frequency is 400
/2
IH
symbolizes I
(min) of the SCL signal)
I2PVKH
Unit
V
V
symbolizes I
2
C timing (I2)
I2C
Notes
—
—
clock
for
2
C
I
57
2
C