MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 148

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

Document Revision History
24 Document Revision History
The following table provides a revision history for this hardware specification.
148
Number
Rev.
9
8
7
6
5
02/2012
09/2010
12/2009
10/2009
04/2011
Date
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
• Updated
• Added
• Updated
• Removed Note from
• Changed the
• Removed table 11.
• Updated the title of
• Corrected the leaded Solder Ball composition in
• Updated
• Updated the Min and Max value of TDO in the valid times row of
• Added
• Updated
• Updated
• In
• Updated
• In
• In
• In
• In
• In
• In
• Updated tMDKHDX in
• Added a reference to Revision 2.1.2.
• Updated
• Added
Version 3.1.x Silicon with Stamped
Stamped Lid.”
Full Lid and Version 3.1.x Silicon with Stamped Lid”
Silicon.
Specifications (Independent of SYSCLK)
“MPC8545E Pinout Listing,” and
is not driven during HRSET* assertion.
delay tMDKHDX (16 × tptb_clk × 8) – 3 — (16 × tptb_clk × 8) + 3” to “MDC to MDIO delay tMDKHDX
(16 × tCCB × 8) – 3 — (16 × tCCB × 8) + 3.”
FC-CBGA and FC-PBGA with Full Lid
avoid falsely triggering ESD circuitry.
for MVREF and 4000 V/s for VDD.
AVDD pins.
35/75 for RX_CLK duty cycle.
Table 37, “MII Management AC Timing
Section 5.1, “Power-On Ramp
Table 13
Table 13
Table 13
Table 13
Table
Figure
Section 14.1, “GPOUT/GPIN Electrical
Section 5.1, “Power-On Ramp
27, “GMII Receive AC Timing Specifications,” changed duty cycle specification from 40/60 to
Section 21.2, “Thermal for Version 2.1.1, 2.1.2, and 2.1.3 Silicon FC-PBGA with Full Lid and
Table
Table 87, “Part Numbering Nomenclature,”
Table
Table
Figure 55, “Mechanical Dimensions and Bottom Surface Nomenclature of the HiCTE
Table 55,
added footnote 2 explaining that VDD voltage ramp rate is intended to control ramp rate of
changed required ramp rate from 545 V/s for MVREF and VDD/XVDD/SVDD to 3500 V/s
deleted ramp rate requirement for XVDD/SVDD.
footnote 1 changed voltage range of concern from 0–400 mV to 20–500mV.
Table 10
56, “Mechanical Dimensions and Bottom Surface Nomenclature of the FC-PBGA with
87, “Part Numbering Nomenclature,” with version 3.0 silicon information.
71, “MPC8548E Pinout Listing,”
87, “Part Numbering Nomenclature” with Ver. 2.1.3 silicon information.
Table 88. Document Revision History
“MII Management AC Timing Specifications.”
Section 21.2, “Thermal for Version 2.1.1, 2.1.2, and 2.1.3 Silicon FC-PBGA with
Section 5.1, “Power-On Ramp
Table
title to “Power Supply Ramp Rate”.
37, “MII Management AC Timing Specifications.”
Table
Rate” added explanation that Power-On Ramp Rate is required to
Lid,” with version 3.0 silicon information.
Substantive Change(s)
Rate.”
and figure notes.
74, “MPC8543E Pinout Listing,” to reflect that the TDO signal
1
” from 4 and 25 to 2 and 10 respectively .
Specifications, modified the fifth row from “MDC to MDIO
Characteristics.”
Table
Table 70, “Package
to include Thermal Version 2.1.3 and Version 3.1.x
Rate”.
with Version 3.1.x silicon information.
72, “MPC8547E Pinout Listing,”
Table 44, “JTAG AC Timing
Parameters”
Freescale Semiconductor
Table
73,