MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 143

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

22.10 Guidelines for High-Speed Interface Termination
This section provides the guidelines for high-speed interface termination when the SerDes interface is
entirely unused and when it is partly unused.
22.10.1 SerDes Interface Entirely Unused
If the high-speed SerDes interface is not used at all, the unused pin must be terminated as described in this
section.
The following pins must be left unconnected (float):
The following pins must be connected to GND:
Pins V28 and M26 must be tied to XV
resistor.
In Rev 2.0 silicon, POR configuration pin cfg_srds_en on TSEC4_TXD[2]/TSEC3_TXD[6] can be used
to power down SerDes block.
22.10.2 SerDes Interface Partly Unused
If only part of the high-speed SerDes interface pins are used, the remaining high-speed serial I/O pins must
be terminated as described in this section.
The following pins must be left unconnected (float) if not used:
The following pins must be connected to GND if not used:
Freescale Semiconductor
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SD_TX[7:0]
SD_TX[7:0]
Reserved pins T22, T23, M20, M21
SD_RX[7:0]
SD_RX[7:0]
SD_REF_CLK
SD_REF_CLK
SD_TX[7:0]
SD_TX[7:0]
Reserved pins: T22, T23, M20, M21
SD_RX[7:0]
SD_RX[7:0]
SD_REF_CLK
It is recommended to power down the unused lane through SRDSCR1[0:7]
register (offset = 0xE_0F08) (This prevents the oscillations and holds the
receiver output in a fixed state.) that maps to SERDES lane 0 to lane 7
accordingly.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
DD
. Pins V27 and M25 must be tied to GND through a 300-
NOTE
System Design Information
143