MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 47

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

Freescale Semiconductor
LGTA/LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output transition (LATCH hold time)
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
Output hold from local bus clock (except LAD/LDP and LALE)
Output hold from local bus clock for LAD/LDP
Local bus clock to output high Impedance (except LAD/LDP and LALE)
Local bus clock to output high impedance for LAD/LDP
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
4. All signals are measured from BV
5. Input timings are measured at the pin.
6. The value of t
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
8. Guaranteed by characterization.
9. Guaranteed by design.
inputs and t
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
for clock one (1). Also, t
to the output (O) going invalid (X) or output hold time.
clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes LCLK
by t
complementary signals at BV
in question for 3.3-V signaling levels.
through the component pin is less than or equal to the leakage current specification.
LBKHKT
.
(first two letters of functional block)(reference)(state)(signal)(state)
LBOTOT
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Table 42. Local Bus Timing Parameters—PLL Bypassed (continued)
is the measurement of the minimum time between the negation of LALE and any change in LAD.
LBKHOX
Parameter
DD
symbolizes local bus timing (LB) for the t
/2.
DD
/2 of the rising edge of local bus clock for PLL bypass mode to 0.4  BV
(first two letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
Symbol
t
t
t
t
t
t
t
t
LBK
t
t
LBKLOV1
LBKLOV2
LBKLOV3
LBKLOV4
LBKLOX1
LBKLOX2
LBKLOZ1
LBKLOZ2
LBK
LBIXKL2
LBOTOT
clock reference (K) goes high (H), in this case
clock reference (K) to go high (H), with respect
1
–1.3
–3.7
–3.7
Min
1.5
—
—
—
—
—
—
LBIXKH1
Max
–0.3
–0.1
0.2
0.2
—
—
—
—
0
0
symbolizes local bus
Unit
DD
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
of the signal
Local Bus
Notes
4, 5
—
6
4
4
4
4
4
7
7
for
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