MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 66

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

High-Speed Serial Interfaces (HSSI)
To illustrate these definitions using real values, consider the case of a CML (current mode logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD or
TD) is 500 mVp-p, which is referred as the single-ended swing for each signal. In this example, since the
differential signaling environment is fully symmetrical, the transmitter output’s differential swing (V
has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between
500 and –500 mV, in other words, V
differential voltage (V
16.2
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK and
SD_REF_CLK for PCI Express and serial RapidIO.
The following sections describe the SerDes reference clock requirements and some application
information.
16.2.1
Figure 39
66
•
•
of a balanced interchange circuit and ground. In this example, for SerDes output, V
V
voltages within a differential pair. In a system, the common mode voltage may often differ from
one component’s output to the other’s input. Sometimes, it may be even different between the
receiver input and driver output circuits within the same component. It is also referred to as the DC
offset.
The supply voltage requirements for XV
SerDes Reference clock receiver reference circuit structure:
A Volts
B Volts
SD_TX
SerDes Reference Clocks
shows a receiver reference diagram of the SerDes reference clocks.
SerDes Reference Clock Receiver Characteristics
+ V
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Figure 38. Differential Voltage Definitions for Transmitter or Receiver
SD_TX
SD_TX or
SD_RX
SD_TX or
SD_RX
DIFFp
= (A + B)/2, which is the arithmetic mean of the two complimentary output
) is 500 mV. The peak-to-peak differential voltage (V
Differential Peak-Peak Voltage, V
OD
is 500 mV in one phase and –500 mV in the other phase. The peak
Differential Swing, V
Differential Peak Voltage, V
DD_SRDS2
ID
are specified in
DIFFpp
or V
OD
DIFFp
= 2*V
= A – B
= |A – B|
DIFFp
(not shown)
Table 1
DIFFp-p
and
V
Freescale Semiconductor
cm
Table
= (A + B)/2
) is 1000 mVp-p.
cm_out
2.
=
OD
)