MPC8543VTANGA Freescale Semiconductor, MPC8543VTANGA Datasheet - Page 138

• Manufacturer Part Number: MPC8543VTANGA
• Description: Microprocessors - MPU PQ3 8543
• Manufacturer: Freescale Semiconductor

Specifications of MPC8543VTANGA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C

System Design Information
22.5
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. All unused active low inputs must be tied to V
required. All unused active high inputs must be connected to GND. All NC (no-connect) signals must
remain unconnected. Power and ground connections must be made to all external V
OV
22.6
The device requires weak pull-up resistors (2–10 k is recommended) on open drain type pins including
I
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in
state under normal operating conditions as most have asynchronous behavior and spurious assertion gives
unpredictable results.
The following pins must not be pulled down during power-on reset: TSEC3_TXD[3], HRESET_REQ,
TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The DMA_DACK[0:1], and TEST_SEL/
TEST_SEL pins must be set to a proper state during POR configuration. See the pinlist table of the
individual device for more details
See the PCI 2.2 specification for all pull ups required for PCI.
22.7
The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a
push-pull single-ended driver type (open drain for I
To measure Z
or GND. Then, the value of each resistor is varied until the pad voltage is OV
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R
OV
other in value. Then, Z
138
2
C pins and PIC (interrupt) pins.
DD
DD
•
•
•
, GV
/2. R
First, the board must have at least 10  10-nF SMT ceramic chip capacitors as close as possible to
the supply balls of the device. Where the board has blind vias, these capacitors must be placed
directly below the chip supply and ground connections. Where the board does not have blind vias,
these capacitors must be placed in a ring around the device as close to the supply and ground
connections as possible.
Second, there must be a 1-µF ceramic chip capacitor from each SerDes supply (SV
to the board ground plane on each side of the device. This must be done for all SerDes supplies.
Third, between the device and any SerDes voltage regulator there must be a 10-µF, low equivalent
series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip
capacitor. This must be done for all SerDes supplies.
Connection Recommendations
Pull-Up and Pull-Down Resistor Requirements
Output Buffer DC Impedance
P
DD
then becomes the resistance of the pull-up devices. R
0
, LV
for the single-ended drivers, an external resistor is connected from the chip pad to OV
Figure
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
DD
, and GND pins of the device.
0
63. Care must be taken to ensure that these pins are maintained at a valid deasserted
= (R
P
+ R
N
)/2.
2
C).
DD
, TV
P
DD
is trimmed until the voltage at the pad equals
, BV
P
and R
DD
, OV
N
are designed to be close to each
DD
DD
, GV
/2 (see
DD
DD
Freescale Semiconductor
, and LV
, TV
Figure
DD
DD
and XV
, BV
DD
61). The
, as
DD
DD
DD
,
)