LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 104

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

September 2010
Introduction
The MachXO™ sysIO™ buffers provide the ability to easily interface with other devices using advanced system I/O
standards. This technical note describes the sysIO standards available and how they can be implemented using
Lattice design software.
sysIO Buffer Overview
The MachXO sysIO interface contains multiple Programmable I/O Cell (PIC) blocks. Each PIC contains two Pro-
grammable I/Os (PIOs). Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”).
In the MachXO256, MachXO1200 and MachXO2280 devices, the PIOs are arranged in groups of six (PIOA, PIOB,
PIOC, PIOD, PIOE, PIOF) on the top and bottom sides of the device and in groups of four (PIOA, PIOB, PIOC,
PIOD) and two (PIOA, PIOB) on the left and right sides of the device. In the MachXO640 device, the PIOs are
arranged in groups of six (PIOA, PIOB, PIOC, PIOD, PIOE, PIOF) on the top and bottom sides and in groups of four
(PIOA, PIOB, PIOC, PIOD) on the left and right sides of the device.
The larger two devices, MachXO1200 and MachXO2280, support single-ended, differential receiver and differential
output sysIO buffers. The two smaller devices, MachXO256 and MachXO640, support single-ended sysIO buffers.
For more information on the architecture of the sysIO buffer please refer to the device data sheets.
Supported sysIO Standards
The MachXO sysIO buffer supports both single-ended and differential standards. Single-ended standards can be
further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2, 1.5,
1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for
drive strength, bus maintenance (weak pull-up, weak pull-down or bus-keeper latch) on I/O buffers. MachXO1200
and MachXO2280 devices also support differential standards like LVDS, RSDS, BLVDS and LVPECL. Table 8-1
lists the sysIO standards supported in the MachXO devices.
Table 8-1. sysIO Standards Supported
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LVCMOS 3.3
LVCMOS 2.5
LVCMOS 1.8
LVCMOS 1.5
LVCMOS 1.2
LVTTL
PCI
LVDS
LVPECL
BLVDS
RSDS
1. Inputs on chip. Outputs are implemented with the addition of external resistors.
2. MachXO1200 and MachXO2280 devices have dedicated LVDS buffers
3. Input on the top bank of the MachXO1200 and MachXO2280 only.
3
Standard
1, 2
1
1
1
3.135
2.375
1.425
3.135
3.135
2.375
3.135
2.375
2.375
Min.
1.71
1.14
8-1
MachXO sysIO Usage Guide
V
CCIO
Typ.
3.3
2.5
1.8
1.5
1.2
3.3
3.3
2.5
3.3
2.5
2.5
(V)
3.465
2.625
1.575
3.465
3.465
2.625
3.465
2.625
2.625
Max.
1.89
1.26
Technical Note TN1091
tn1091_01.5