LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 208

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
Design Partitioning
By effectively partitioning the design, a designer can reduce overall run time and improve synthesis results. Here
are some recommendations for design partitioning.
Maintain Synchronous Sub-blocks by Registering All Outputs
It is suggested to arrange the design boundary such that the outputs in each block are registered. Registering out-
puts helps the synthesis tool to consider the implementation of the combinatorial logic and registers into the same
logic block. Registering outputs also makes the application of timing constraints easier since it eliminates possible
problems with logic optimization across design boundaries. Single clock is recommended for each synchronous
block because it significantly reduces the timing consideration in the block. It leaves the adjustment of the clock
relationships of the whole design at the top level of the hierarchy. Figure 13-1 shows an example of synchronous
blocks with registered outputs.
Figure 13-1. Synchronous Blocks with Registered Outputs
Keep Related Logic Together in the Same Block
Keeping related logic and sharable resources in the same block allows the sharing of common combinatorial terms
and arithmetic functions within the block. It also allows the synthesis tools to optimize the entire critical path in a
single operation. Since synthesis tools can only effectively handle optimization of certain amounts of logic, optimi-
zation of critical paths pending across the boundaries may not be optimal. Figure 13-2 shows an example of merg-
ing sharable resource in the same block.
Figure 13-2. Merge Sharable Resource in the Same Block
Separate Logic with Different Optimization Goals
Separating critical paths from non-critical paths may achieve efficient synthesis results. At the beginning of the proj-
ect, one should consider the design in terms of performance requirements and resource requirements. If there are
• Memory blocks should be kept separate from other code
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A
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MUX
MUX
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13-2
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
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