LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 137

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
Table 9-6. MachXO Dual Port RAM Attributes
The True Dual Port RAM (RAM_DP_TRUE) can be configured as NORMAL, READ BEFORE WRITE or WRITE
THROUGH modes. Each of these modes affects what data comes out of port Q of the memory during the write
operation followed by the read operation at the same memory location. Detailed discussions of the WRITE modes
and the constraints of the True Dual Port can be found in Appendix A.
Additionally users can select to enable the output registers for RAM_DP_TRUE. Figures 9-16 to 9-21 show the
internal timing waveforms for the True Dual Port RAM (RAM_DP_TRUE) with these options.
DATA_WIDTH_A Data Word Width Port A
DATA_WIDTH_B Data Word Width Port B
REGMODE_A
REGMODE_B
RESETMODE
CSDECODE_A
CSDECODE_B
WRITEMODE_A
WRITEMODE_B
ENABLE GSR
Attribute
Register Mode (Pipelining)
for Port A
Register Mode (Pipelining)
for Port B
Chip Select Decode
for Port A
Chip Select Decode
for Port B
Read / Write Mode
for Port A
Read / Write Mode
for Port B
Enables Global Set Reset
Selects the Reset type
Description
1, 2, 4, 9, 18
1, 2, 4, 9, 18
NOREG, OUTREG
NOREG, OUTREG
ASYNC, SYNC
0b000, 0b001, 0b010, 0b011,
0b100, 0b101, 0b110, 0b111
000, 001, 010, 011,
100, 101, 110, 111
NORMAL, WRITETHROUGH,
READBEFOREWRITE
NORMAL, WRITETHROUGH,
READBEFOREWRITE
ENABLE, DISABLE
9-14
Values
Memory Usage Guide for MachXO Devices
ENABLED
NORMAL
NORMAL
Default
NOREG
NOREG
ASYNC
Value
000
000
18
18
User Selectable through
IPexpress
YES
YES
YES
YES
YES
YES
YES
YES
NO
NO