LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 130

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
The Input Data and the Address Control is always registered, as the hardware only supports the clocked write
operation for the EBR based RAMs. The check box Enable Output Registers, inserts the output registers in the
Read Data Port, as the output registers are optional for the EBR-based RAMs.
Users have the option to set the Reset Mode as Asynchronous Reset or Synchronous Reset. Enable GSR can be
checked to be enable the Global Set Reset.
Users can also pre-initialize their memory with the contents specified in the Memory File. It is optional to provide
this file in the RAM; however for ROM, the Memory File is required. These files can be of Binary, Hex or Addresses
Hex format. The details of these formats are discussed in the Initialization File section of this document.
At this point, users can click the Generate button to generate the module they have customized. A VHDL or Verilog
netlist is then generated and placed in the specified location. Users can incorporate this netlist in their designs.
Another important button is the Load Parameters button. IPexpress stores the parameters the user has specified
in an <module_name>.lpc file. This file is generated along with the module. Users can click on the Load Parameter
button to load the parameters of a previously generated module to re-visit or make changes to them.
Once the module is generated, user can either instantiate the *.lpc or the Verilog-HDL/ VHDL file in top-level mod-
ule of their design.
The various memory modules, both EBR and Distributed, are discussed in detail in this document.
Memory Modules
Single Port RAM (RAM_DQ) – EBR Based: The EBR blocks in the MachXO devices can be configured as Single
Port RAM or RAM_DQ. IPexpress allows users to generate the Verilog-HDL or VHDL along EDIF netlist for the
memory size, as per design requirements.
IPexpress generates the memory module as shown in Figure 9-8.
Figure 9-8. Single Port Memory Module Generated by IPexpress
Since the device has a number of EBR blocks, the generated module makes use of these EBR blocks, or primi-
tives, and cascades them to create the memory sizes specified by the user in the IPexpress GUI. For memory sizes
smaller than an EBR block, the module will be created in one EBR block. For memory sizes larger than one EBR
block, multiple EBR blocks can be cascaded in depth or width (as required to create these sizes).
In Single Port RAM mode, the input data and address for the ports are registered at the input of the memory array.
The output data of the memory is optionally registered at the output.
ClockEn
Address
Reset
Clock
Data
WE
EBR-based Single Port
9-7
RAM_DQ
Memory
Memory Usage Guide for MachXO Devices
Q