LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 114

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
Tristate All (TSALLPAD)
All MachXO devices have a dedicated TSALLPAD pin that is used to enable or disable the tristate control to all the
output buffers. By default, the pin will function as an I/O unless programmed to be a TSALLPAD. This signal also
has programmable global polarity control. By default, the polarity is active high. This global tristate control signal
can also be generated using user logic.
When the TSALLPAD is enabled, the software will implement the tristate control using the TSALL software primi-
tive. The polarity control of the TSALLPAD will control the polarity of TSALL.
When TSALLPAD is not used in the design, but is required for test purposes, the TSALL primitive can be instanti-
ated in the HDL and the TSALLPAD is connected to the input of this primitive.
Differential I/O Implementation
MachXO devices support a variety of differential standards, as detailed in the following sections.
LVDS (MachXO1200 and MachXO2280)
True LVDS (LVDS25) drivers are available on 50% of the I/Os on the left and right sides of the MachXO1200 and
MachXO2280 devices. LVDS input support is available on all sides of the MachXO1200 and MachXO2280 devices.
LVDSE
The single-ended sysIO buffer pairs in all the MachXO devices support LVDS output drivers using complementary
LVCMOS drivers with external resistors (LVDS25E) on all four sides of the device.
The MachXO1200 and MachXO2280 devices also support LVDSE inputs on all four sides of the device.
Please refer to the
BLVDS
All single-ended sysIO buffer pairs in all the MachXO devices support Bus-LVDS output driver using complemen-
tary LVCMOS drivers with external resistors on all the four sides of the device.
The MachXO1200 and MachXO2280 devices also support BLVDS inputs on all four sides of the device.
Please refer to the
RSDS
All single-ended sysIO buffer pairs in all the MachXO devices support RSDS output driver using complementary
LVCMOS drivers with external resistors.
The MachXO1200 and MachXO2280 devices also support RSDS inputs on all four sides of the device.
Please refer to the
LVPECL
All single-ended sysIO buffers pairs in all the MachXO devices support LVPECL output driver using complementary
LVCMOS drivers with external resistors.
The MachXO1200 and MachXO2280 devices also support LVPECL inputs on all four sides of the device.
Please refer to the
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet:
[phone] (Outside North America)
[e-mail]
www.latticesemi.com
MachXO Family Data Sheet
MachXO Family Data Sheet
MachXO Family Data Sheet
MachXO Family Data Sheet
for a detailed explanation of these LVDS implementations.
for a detailed explanation of BLVDS implementation.
for a detailed explanation of RSDS implementation.
for a detailed explanation of LVPECL implementation.
8-11
MachXO sysIO Usage Guide