LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 153

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
Distributed Single Port RAM (Distributed_SPRAM) – PFU Based
PFU based Distributed Single Port RAM is created using the 4-input LUT (Look-Up Table) available in the PFU.
These LUTs can be cascaded to create larger distributed memory sizes.
Figure 9-31 shows the Distributed Single Port RAM module as generated by IPexpress.
Figure 9-31. Distributed Single Port RAM Module Generated by IPexpress
The generated module makes use of the 4-input LUT available in the PFU. Additional logic such as clock and reset
is generated by utilizing the resources available in the PFU.
Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn) are not available in the hardware primi-
tive. These are generated by the IPexpress when the user wants the to enable the output registers in the IPexpress
configuration.
The various ports and their definitions are listed in Table 9-15. The table lists the corresponding ports for the mod-
ule generated by IPexpress and for the primitive.
Table 9-15. PFU-based Distributed Single Port RAM Port Definitions
Ports such as Clock Enable (ClockEn) are not available in the hardware primitive. These are generated by IPex-
press when the user wishes the to enable the output registers in the IPexpress configuration.
Users have the option of enabling the output registers for Distributed Single Port RAM (Distributed_SPRAM). Fig-
ures 9-32 and 9-33 show the internal timing waveforms for the Distributed Single Port RAM (Distributed_SPRAM)
with these options.
Generated Module
Port Name in
ClockEn
Address
Reset
Clock
Data
WE
Q
ClockEn
Address
Port Name in the
Reset
Clock
Data
PFU Primitive
WE
DO[1:0]
AD[3:0]
DI[1:0]
WRE
CK
—
—
Distributed Single Port
9-30
PFU based
Memory
Memory Usage Guide for MachXO Devices
Clock Enable
Write Enable
Description
Data Out
Address
Data In
Reset
Clock
Q
Rising Clock Edge
Active State
Active High
Active High
Active High
—
—
—