LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 131

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
The various ports and their definitions for the Single Port Memory are listed in Table 9-1. The table lists the corre-
sponding ports for the module generated by IPexpress and for the EBR RAM_DQ primitive.
Table 9-1. EBR-based Single Port Memory Port Definitions
Reset (or RST) resets only the input and output registers of the RAM. It does not reset the contents of the memory.
Chip Select (CS) is a useful port in the EBR primitive when multiple cascaded EBR blocks are required by the
memory. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-bit bus,
so it can cascade eight memories easily. If the memory size specified by the user requires more than eight EBR
blocks, the ispLEVER or Diamond software automatically generates the additional address decoding logic which is
implemented in the PFU (external to the EBR blocks).
Each EBR block consists of 9,216 bits of RAM. The values for x (address) and y (data) for each EBR block for the
devices are listed in Table 9-2.
Table 9-2. Single Port Memory Sizes for 9K Memories in MachXO
Table 9-3 shows the various attributes available for the Single Port Memory (RAM_DQ). Some of these attributes
are user selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A.
Generated Module
Port Name in the
ClockEn
Address
Reset
Clock
Data
WE
—
Q
Memory Size
Single Port
512 x 18
256 x 36
8K x 1
4K x 2
2K x 4
1K x 9
EBR Block Primitive
Input Data
Port Name in the
DI[17:0]
DI[35:0]
DI[1:0]
DI[3:0]
DI[8:0]
DI
DO[y:0]
AD[x:0]
CS[2:0]
DI[y:0]
CLK
RST
WE
CE
9-8
Memory Usage Guide for MachXO Devices
Output Data
DO[17:0]
DO[35:0]
DO[1:0]
DO[3:0]
DO[8:0]
DO
Clock Enable
Write Enable
Address Bus
Description
Chip Select
Data Out
Data In
Reset
Clock
[MSB:LSB]
Address
AD[12:0]
AD[11:0]
AD[10:0]
AD[9:0]
AD[8:0]
AD[7:0]
Rising Clock Edge
Active State
Active High
Active High
Active High
—
—
—
—