LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 209

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

HDL Synthesis Coding Guidelines
Lattice Semiconductor
for Lattice Semiconductor FPGAs
two portions of a block, one that needs to be optimized for area and a second that needs to be optimized for speed,
they should be separated into two blocks. By doing this, different optimization strategies for each module can be
applied without being limited by one another.
Keep Logic with the Same Relaxation Constraints in the Same Block
When a portion of the design does not require high performance, this portion can be applied with relaxed timing
constraints such as “multicycle” to achieve high utilization of device area. Relaxation constraints help to reduce
overall run time. They can also help to efficiently save resources, which can be used on critical paths. Figure 13-3
shows an example of grouping logic with the same relaxation constraint in one block.
Figure 13-3. Logic with the Same Relaxation Constraint
A
B
A
FF1
FF2
FF1
FF2
Keep Instantiated Code in Separate Blocks
It is recommended that the RAM block in the hierarchy be left in a separate block (Figure 13-4). This allows for easy
swapping between the RAM behavioral code for simulation, and the code for technology instantiation. In addition,
®
this coding style facilitates the integration of the ispLEVER
IPexpress™ tool into the synthesis process.
Figure 13-4. Separate RAM Block
Top
RAM
Controller
Register File
State Machine
Counter
Keep the Number FPGA Gates at 30 to 80 PFUs Per Block
This range varies based on the computer configuration, time required to complete each optimization run, and the
targeted FPGA routing resources. Although a smaller block methodology allows more control, it may not produce
the most efficient design since it does not provide the synthesis tool enough logic to apply “Resource Sharing”
algorithms. On the other hand, having a large number of gates per block gives the synthesis tool too much to work
on and causes changes that affect more logic than necessary in an incremental or multi-block design flow.
State Encoding Methodologies for State Machines
There are several ways to encode a state machine, including binary encoding, gray-code encoding and one-hot
encoding. State machines with binary or gray-code encoded states have minimal numbers of flip-flops and wide
combinatorial functions, which are typically favored for CPLD architectures. However, most FPGAs have many flip-
flops and relatively narrow combinatorial function generators. Binary or gray-code encoding schemes can result in
inefficient implementation in terms of speed and density for FPGAs. On the other hand, one-hot encoded state
machine represents each state with one flip-flop. As a result, it decreases the width of combinatorial logic, which
matches well with FPGA architectures. For large and complex state machines, one-hot encoding usually is the
preferable method for FPGA architectures. For small state machines, binary encoding or gray-code encoding may
be more efficient.
There are many ways to ensure the state machine encoding scheme for a design. One can hard code the states in
the source code by specifying a numerical value for each state. This approach ensures the correct encoding of the
state machine but is more restrictive in the coding style. The enumerated coding style leaves the flexibility of state
machine encoding to the synthesis tools. Most synthesis tools allow users to define encoding styles either through
13-3