LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 135

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
Figure 9-14. Single Port RAM Timing Waveform - WRITE THROUGH Mode, with Output Registers
True Dual Port RAM (RAM_DP_TRUE) – EBR Based
The EBR blocks in MachXO devices can be configured as True-Dual Port RAM or RAM_DP_TRUE. IPexpress
allows users to generate the Verilog-HDL, VHDL or EDIF netlists for various memory sizes depending on design
requirements.
IPexpress generates the memory module as shown in Figure 9-15.
Figure 9-15. True Dual Port Memory Module generated by IPexpress
The generated module makes use of these EBR blocks or primitives. For memory sizes smaller than an EBR block,
the module will be created in one EBR block. When the specified memory is larger than one EBR block, multiple
EBR blocks can be cascaded in depth or width (as required to create these sizes).
In True Dual Port RAM mode, the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output.
The various ports and their definitions for Single Port Memory are in Table 9-4. The table lists the corresponding
ports for the module generated by IPexpress and for the EBR RAM_DP_TRUE primitive.
ClockEn
Address
Reset
Clock
Data
WE
Q
t
t
SUADDR_EBR
SUDATA_EBR
t
SUCE_EBR
Data_0
Add_0
Invalid Data
ClockEnA
AddressA
DataInA
ResetA
ClockA
t
t
HADDR_EBR
HDATA_EBR
WrA
QA
Data_1
Add_1
EBR-based True Dual
t
SUWREN_EBR
RAM_DP_TRUE
Port Memory
9-12
Data_0
Data_2
Memory Usage Guide for MachXO Devices
t
HWREN_EBR
t
COO_EBR
Data_1
Data_3
Add_0
ClockB
ClockEnB
ResetB
WrB
AddressB
DataInB
QB
Data_2
Data_4
t
HCE_EBR
Data_3