LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 158
LCMXO2280C-5TN144C
Manufacturer Part Number
LCMXO2280C-5TN144C
Description
MACHXO PLD FLASH, SCRAM 1.8V, SMD
Manufacturer
LATTICE SEMICONDUCTOR
Series
MachXOr
Datasheet
1.LCMXO1200C-5TN144C.pdf
(244 pages)
Specifications of LCMXO2280C-5TN144C
Cpld Type
FLASH
No. Of Macrocells
1140
No. Of I/o's
113
Propagation Delay
3.6ns
Global Clock Setup Time
1.1ns
Frequency
600MHz
Supply Voltage Range
1.71V To 3.465V
Operating
RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2280C-5TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LCMXO2280C-5TN144C
Manufacturer:
LATTICE/莱迪斯
Quantity:
20 000
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Lattice Semiconductor
Distributed ROM (Distributed_ROM) – PFU Based
PFU-based Distributed ROM is also created using the 4-input LUT (Look-Up Table) available in the PFU. These
LUTs can be cascaded to create larger distributed memory sizes.
Figure 9-37 shows the Distributed ROM module as generated by IPexpress.
Figure 9-37. Distributed ROM Generated by IPexpress
The generated module makes use of the 4-input LUT available in the PFU. Additional logic like clock and reset is
generated by utilizing the resources available in the PFU.
Ports such as Out Clock (OutClock) and Out Clock Enable (OutClockEn) are not available in the hardware primi-
tive. These are generated by IPexpress when the user wants the to enable the output registers in the IPexpress
configuration.
The various ports and their definitions are listed in Table 9-17. The table lists the corresponding ports for the mod-
ule generated by IPexpress and for the primitive.
Table 9-17. PFU-based Distributed ROM Port Definitions
Users have the option of enabling the output registers for Distributed ROM (Distributed_ROM). Figures 9-38 and 9-
39 show the internal timing waveforms for the Distributed ROM with these options.
Figure 9-38. PFU-Based ROM Timing Waveform – Without Output Registers
Generated Module
Port Name in
OutClockEn
OutClock
Address
Reset
Address
Q
Q
Invalid Data
t
OutClockEn
SUADDR_PFU
PFU Block Primitive
OutClock
Port Name in the
Address
Reset
AD[3:0]
Add_0
DO
—
—
—
t
HADDR_PFU
t
CORAM_PFU
Distributed ROM
9-35
PFU-based
Data_0
Add_1
Memory Usage Guide for MachXO Devices
Out Clock Enable
Description
Out Clock
Data Out
Address
Reset
Data_1
Add_2
Q
Rising Clock Edge
Data_2
Active State
Active High
Active High
—
—
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