LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 167

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
Figure 10-4. MACHXO PLL Primitive Symbols
Table 10-2. MachXO PLL I/O Definitions
PLL Attributes Definitions
The MachXO PLL utilizes several attributes that allow the configuration of the PLL through source constraints. This
section details these attributes and their usage.
Table 10-3. MachXO PLL User Attributes
CLKI Frequency (MHz)
CLKI Frequency (MHz)
CLKOP Frequency (MHz)
CLKOK Frequency (MHz)
CLKOP Frequency 
Tolerance (%)
CLKI Divider Setting
CLKFB Divider Setting
CLKOP Divider Setting
CLKOK Divider Setting
Fine Delay Adjust
Coarse Phase Shift
Selection (O)
CLKI
CLKFB
RST
CLKOP
CLKOS
CLKOK
LOCK
CLKINTFB
DDAMODE
DDAIZR
DDAILAG
DDAIDEL[2:0}
Signal
Attributes
I/O
O
O
O
O
O
I
I
I
I
I
I
I
MM GUI
Access
General routing or dedicated global clock input pad.
From general routing, clock tree, internal feedback from CLKOP or dedicated external feedback
pad.
“1” to reset PLL counters.
PLL output to clock tree (CLKOK divider, low speed, output).
Internal feedback source. CLKOP divider output before CLOCK TREE.
DDA delay.
PLL output clock to clock tree (no phase shift).
PLL output clock to clock tree (phase shifted/duty cycle changed).
“1” indicates PLL LOCK to CLKI, asynchronous signal.
DDA Mode. “1” Pin control (dynamic), “0”: Fuse Control (static).
DDA Delay Zero. “1”: delay = 0, “0”: delay = on.
DDA Lag/Lead. “1”: Lead, “0”: Lag.
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
FREQUENCY_PIN_CLKOP
FREQUENCY_PIN_CLKOK
FREQUENCY_PIN_CLKI
Attribute Name
CLKOP_DIV
CLKOK_DIV
CLKFB_DIV
PHASEADJ
CLKI_DIV
RST
CLKI
CLKFB
DDAMODE
DDAIZR
DDAILAG
DDAIDEL2
DDAIDEL1
DDAIDEL0
FDEL
FIN
7
4
EHXPLLC
10-5
Preference
CLKINTFB
Support
Editor
CLKOP
CLKOS
CLKOK
Description
LOCK
N
N
N
N
N
N
N
N
N
Y
N
0.0,0.1,0.2,0.5,1.0,2.0,5.0,10.0
2,4,6,..,126,128
Design and Usage Guide
0, 45, 90...315
MachXO sysCLOCK PLL
1 to 16
1 to 16
Note 6
Note 6
Note 6
Note 6
Note 3
-8 to 8
Value
8 (Note 2)
Default
Value
100
100
100
0.0
50
1
1
2
0
0